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256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 22: Power-Up Specifications
Symbol
Parameter
V CC HIGH to V CCQ HIGH
V CC HIGH to rising edge of RST#
V CCQ HIGH to rising edge of RST#
RST# HIGH to chip enable LOW
RST# HIGH to write enable LOW
Legacy
–
t VCS
t VIOS
t RH
–
JEDEC
t VCHVCQH
t VCHPH
t VCQHPH
t PHEL
t PHWL
Min
0
300
0
50
150
Unit
μs
μs
μs
ns
ns
Notes
1
2
2
Notes:
1. V CC and V CCQ ramps must be synchronized during power-up.
2. If RST# is not stable for t VCS or t VIOS, the device will not allow any READ or WRITE oper-
ations, and a hardware reset is required.
Figure 13: Power-Up Timing
t VCHVCQH
V CC
V CCQ
t RH
CE#
t VIOS
RST#
t VCS
WE#
t PHWL
PDF: 09005aef849b4b09
m29ew_256mb_2gb.pdf - Rev. B 8/12 EN
53
Micron Technology, Inc. reserves the right to change products or specifications without notice.
? 2012 Micron Technology, Inc. All rights reserved.
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